This invention generally relates to semiconductor devices. Especially, this invention relates to a semiconductor integrated circuit device that includes a non-volatile semiconductor memory device. Further, this invention is related to fabrication process of a semiconductor integrated circuit that uses a plural power supply voltages.
A flash memory is a non-volatile semiconductor memory device that stores information in a floating-gate electrode in the form of electric charges. It has a simple device construction. Therefore, it is suited to construct a large-scale integrated circuit device.
In a flash memory, writing and erasing of information is done by injection and pulling out of hot-carriers to or from a floating-gate electrode through a tunneling insulation film. In this operation, a high voltage is required for producing hot-carriers. For this purpose, a boosting circuit is provided in a peripheral circuit that cooperates with a memory cell for boosting a power supply voltage. The transistor used in such a peripheral circuit is required to operate at high voltage.
Meanwhile, it is recently practiced to construct such a flash memory device together with a high-speed logic circuit on a common semiconductor substrate in the form of semiconductor integrated circuit. The transistors that are used in such a high-speed logic circuit operate at low voltage. Because of this, there is a need to use a plural power supply voltages in such a semiconductor integrated circuit.
FIG. 1A-1Q are diagrams showing the fabrication process of a conventional semiconductor integrated circuit including a flash memory. The semiconductor integrated circuit uses plural power supply voltages.
FIG. 1A is referred to.
A flash-memory cell region A, a low-voltage transistor region B and a high-voltage transistor region C are defined on a Si substrate 11 that carries thereon a field oxide film or STI structure or other device isolation structure (not shown).
In the step of FIG. 1A, a thermal oxidation processes is applied to the surfaces of the Si substrate 11 at 800-1100° C., and a tunneling oxide film 12A is formed in regions A-C with a thickness of 10 nm. Furthermore, in the step of FIG. 1B, an amorphous silicon film 13 doped with P (phosphor) is formed on the tunneling oxide film 12A with a thickness of 8-12 nm, and an insulation film 14 having an ONO structure is formed on the tunneling oxide film 12A. The ONO insulation film 14 is formed of an SiO2 film 14a deposited on the amorphous silicon film 13 by a CVD process with a thickness of 5-9 nm and an SiN film 14b deposited on the SiO2 film 14a with a thickness of 6-10 nm by a CVD process. Further, a thermal oxide film 14c is formed on the SiN film 14b with a thickness of 3-10 nm. The ONO film thus formed has an excellent leakage current characteristic.
Next, a resist pattern 15A is formed on the flash-memory cell region A in the process of FIG. 1C. Using the resist pattern 15A as a mask, the ONO film 14, the amorphous silicon film 13 and also the tunneling insulation film 12A on Si substrate 11 are removed in the low-voltage transistor region B and in the high-voltage transistor region C. In this way, the surface of Si substrate 11 is exposed in the low-voltage transistor region B and also in the high-voltage transistor region C. In the foregoing removal process of the tunneling insulation film 12A, a wet etching process using an HF etchant is implemented. As a result, the surface of the Si substrate 11 is exposed to the HF etchant in regions B and C.
Next, the resist pattern 15A is removed in the step of FIG. 1D. Furthermore, a thermal oxidation process is applied with a temperature of 800-1100° C. Thus, the Si substrate 11 is covered, in the regions B and C, with a thermal oxide film 12C with the thickness of 8-50 nm.
Further, a next resist pattern 15B is formed on the Si substrate 11 in the step of FIG. 1E so as to cover the ONO film 14 in the flash-memory cell region A and also the thermal oxide film 12C in the high-voltage transistor region C. Using the resist pattern 15B as a mask, the thermal oxide film 12C on the Si substrate 11 is removed by an HF treatment in the low-voltage transistor region B. As a result, the surface of Si substrate 11 is exposed. In the step of FIG. 1E, the surface of the Si substrate 11 experiences the HF treatment in region B for the second time.
The resist pattern 15B is removed in the process of FIG. 1F. Further, a thermal oxide film 12B is formed on the Si substrate 11 exposed in the region B by a thermal oxidation processes at 800-1100° C., with a thickness of 1.5-8 nm. As a result of the thermal oxidation process in the step of FIG. 1F for forming the thermal oxide film 12B, it should be noted that there occurs an increase of thickness in the thermal oxide film 12C formed on the high-voltage transistor region C.
Next, in the step of FIG. 1G, an amorphous silicon film 16 doped with P is deposited on the structure of FIG. 1F by a CVD process with a thickness of 120-250 nm. Next, the amorphous silicon film 16, the ONO film 14 and the amorphous silicon film 13 are patterned consecutively in the process of FIG. 1H while using the resist pattern 17A as a mask. In this way, a stacked gate electrode structure 16F of a flash memory, including the amorphous silicon pattern 13A, the ONO pattern 14A and the amorphous silicon pattern 16A, is formed in the flash-memory cell region A. In this stacked gate electrode structure 16F, the amorphous silicon pattern 13A functions as a floating-gate electrode. In the process of FIG. 1G, it is as well possible to form a silicide film of WSi or CoSi on the amorphous silicon film 16 according to the needs.
Next, in the step of FIG. 1I, the resist pattern 17A is removed, and a new resist pattern 17B is formed so as to cover the flash-memory cell region A. While using the resist pattern 17B as a mask, the amorphous silicon film 16 is patterned in the low-voltage transistor region B and in the high-voltage transistor region C, and a gate electrode 16B of the low-voltage transistor is formed to region B. Further, a gate electrode 16C of the high-voltage transistor is formed in the region C.
Next, the resist pattern 17B is removed in the step of FIG. 1J, and a protective oxide film 18 is formed so as to cover the stacked gate electrode structure 16F in the flash-memory cell region A and the gate electrode 16B in the low-voltage transistor region B and the gate electrode 16C in the high-voltage transistor region C by a thermal oxidation processes at 800-900° C.
Next, in the step of FIG. 1K, a resist pattern 19A is formed on the structure of FIG. 1J so as to cover the low-voltage transistor region B and the high-voltage transistor region C and so as to cover the flash-memory cell region A partially. Next, while using the resist pattern 19A and also the stacked gate electrode 16F as a mask, an ion implantation process of P+ is conducted under an accelerating voltage of typically 50-80 keV with a dose of 0.5×1014-3×1014 cm−2. As a result, an n-type diffusion region 11a is formed in the Si substrate 11 adjacent to the stacked gate electrode 16F.
In the step of FIG. 1K, an ion implantation process of As+ is conducted while using the resist pattern 19A as a mask under an accelerating voltage of typically 30-50 keV with a dose of 2×1015-6×1015 cm−2, and another n-type diffusion region 11b is formed inside the n-type diffusion region 11a. In the step of FIG. 1K, it should be noted that the low-voltage transistor region B and the high-voltage transistor region C are covered by the resist pattern 19A. Thus, there occurs no ion implantation in these regions.
Next, in the step of FIG. 1L, the resist pattern 19A is removed and a resist pattern 19B is newly formed so as to expose the region A and so as to cover the regions B and C. In the step of FIG. 1L, the resist pattern 19B is used as a mask and an ion implantation of As+ is conducted under an accelerating voltage of 30-50 keV with a dose of 5×1014-2×1015 cm−2. As a result, the impurity concentration level in the n-type diffusion region 11b is increased and another n-type diffusion region 11c is formed in the flash memory region A while using the stacked gate structure 16F as a self-aligned mask.
Next, the resist pattern 19B is removed in the step of FIG. 1M, and the resist pattern 19C is formed on the Si substrate 11 so as to expose the low-voltage transistor region B selectively. Furthermore, in the step of FIG. 1M, a p-type impurity element or an n-type impurity element is introduced by an ion implantation process while using the resist pattern 19C as a mask, and a pair of LDD diffusion regions 11d are formed in region B of the Si substrate 11 at both lateral sides of the gate electrode 16B.
Next, in the step of FIG. 1N, the resist pattern 19C is removed, and a resist pattern 19D is formed on Si substrate 11 so as to expose the high-voltage transistor region C selectively. Further, an impurity element of p-type or n-type is introduced in the step of FIG. 1N while using the resist pattern 19D as a mask, and a pair of LDD diffusion regions 11e are formed in the Si substrate 11 at both lateral sides of the gate electrode 16C.
Further, in the process of FIG. 10, sidewall insulation film 16s are formed on both sidewall surfaces of the stacked gate electrode 16F, the gate electrode 16B and the gate electrode 16C by deposition and etch back of a CVD oxide film, and in the step of FIG. 1P, a resist pattern 19E is formed such that the resist pattern 19E covers the flash-memory cell region A and exposes the low-voltage transistor region B and the high-voltage transistor region C. Further, a p-type impurity element or an n-type impurity element is introduced by an ion implantation process while using the resist pattern 19E and the gate electrodes 16B and 16C as a mask, and diffusion regions 11f of p+-type or n+-type are formed in the Si substrate 11 outside the gate electrode 16B in the region B. Similarly, diffusion regions 11g of p+-type or n+-type are formed in the Si substrate in correspondence to the region C outside of the gate electrode 16C. On the surface of the diffusion regions 11f or 11g, it is also possible to form a low-resistance silicide films such as TiSi or CoSi by a salicide process.
Next, in the process of FIG. 1Q, an interlayer insulation film 20 is formed on the Si substrate 11 so as to cover the regions A-C continuously, and contact holes are formed the interlayer insulation film 20 so as to expose the diffusion regions 11b and 11c in the region A. A W plug 20A is formed in the contact hole. Similarly, a contact hole exposing the diffusion region 11f is formed in the region B, and a W plug 20B is formed in the contact hole thus formed. Further, a contact hole exposing the diffusion region 11g is formed in the interlayer insulation film 20 in correspondence to the region C, and a W plug 20C is formed in the contact hole thus formed.
In the case of fabricating such a semiconductor integrated circuit, in which a flash memory including a peripheral circuit and a high-speed logic circuit are integrated, according to the process of FIGS. 1A-1Q, one encounters the following problems. In the process of FIG. 1B, the amorphous silicon film 13 and the ONO film 14 are formed on a flat surface of the Si substrate in the flash-memory cell region A or in the low-voltage transistor region B or in the high-voltage transistor region C as shown in FIGS. 2A, 2B and 2C.
Thus, in the process of removing the tunneling insulation film 12A and the amorphous silicon film 13 and the ONO film 14 from regions B and C in the step of FIG. 1C, the depression is etched by HF in region B and C as is shown in the enlarged view of FIGS. 3A-3C, and the depth of the depression increases slightly in the regions B and C.
Further, in the process of FIG. 1D, the bottom of the depression goes up a little as a result of formation of the thermal oxide film 12B in the regions B and C as shown in detail in FIGS. 4A-4C. As a result, there appears a step at the boundary between the depression and the field oxide film 11F surrounding the depression. With the removal of the thermal oxide film 12B by an HF etching treatment from the region B in the process of FIG. 1E, there inevitably appears a step corresponding to the step of FIGS. 4B and 4C on the surface of the Si substrate as is enclosed by a circle in FIGS. 5B and 5C at the boundary between the region B and the field oxide film 11F. Contrary to this, the flash-memory cell region A remains flat as shown in FIG. 5A.
A similar step is formed also at the boundary between the Si substrate surface forming the low-voltage transistor region B and the field oxide film 11F as shown in FIGS. 6B and 6C with the process of FIG. 1F forming the thermal oxide film 12B on the region B. As a result, the thickness of the thermal oxide film 12B is decreased inevitably in such a stepped part. On the other hand, the surface of the substrate 11 remains flat in the flash-memory cell region A as shown in FIG. 6A. Thus, when the gate electrode 16 is formed on such a structure in which the thickness of the thermal oxide film 12B is decreased in such a stepped part in the process of FIG. 1G to form a low-voltage transistor, the desired operational characteristics are not obtained from such a transistor.
A similar problem arises also in a semiconductor integrated circuit shown in FIGS. 7A and 7B that uses an STI structure 11G as the device isolation structure, in place of the field oxide film 11F. The problem of decrease of the film thickness of the insulation film has been known in STI structures in which the device isolation trench forms a steep angle at the top part thereof with respect to the substrate principal surface. Under these circumstances, the process of FIGS. 1A-1Q deteriorates this problem worse.
On the other hand, there are demands in these days to use plural power supply voltages in a semiconductor integrated circuit that includes a flash memory device. In such multiple voltage semiconductor integrated circuit devices, it is necessary to form MOS transistors such that the MOS transistors have a gate insulation film of optimal thickness in correspondence to the respective power supply voltages.
FIGS. 8A-8M show one possible expansion of the process of FIGS. 1A-1Q for the case the semiconductor integrated circuit includes a low-voltage transistor, a mid-voltage transistor and a high-voltage transistor in addition to the flash memory cell. It should be noted that the process of FIGS. 8A-8M are not used actually due to the problems that will be explained later. In FIGS. 8A-8M, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
FIG. 8A is referred to.
A mid-voltage transistor region D is defined on the surface of the Si substrate 11 by the field oxide film in addition to the flash-memory cell region A, the low-voltage transistor region B and the high-voltage transistor region C, and the tunneling oxide film 12A is formed uniformly on the regions A-D in the step of FIG. 8A similarly to the step of FIG. 1A.
Next, in the step of FIG. 8B corresponding to the step of FIG. 1B, the amorphous silicon film 13 and the ONO film 14 are formed consecutively on the tunneling oxide film 12A in each of the regions A-D. Next, in the step of FIG. 8C corresponding to the step of FIG. 1C, the tunneling oxide film 12A, the amorphous silicon film 13 and the ONO film 14 are removed from the part other than flash-memory cell region A while using the resist pattern 15A as a mask, and the surface of the Si substrate 11 is exposed. In the step of FIG. 8C, the surface of Si substrate 11 is exposed to HF before removing the tunneling oxide film 12A in each of the regions B-D.
Next, in the step of FIG. 8D, the Si substrate 11 is subjected to a thermal oxidizing process similar to the process of FIG. 1D, and the thermal oxide film 12C is formed in each of the regions B-D so as to cover the surface of the Si substrate 11.
Next, in the step of FIG. 8E, the resist pattern 15D is formed on the structure of FIG. 8D except for the region D, and an HF treatment is applied while using the resist pattern 15D as a mask. As a result, the thermal oxide film 12C is removed from the surface of Si substrate 11 in the region D.
Next, in the step of FIG. 8F, the resist pattern 15D is removed and a thermal oxidation processes is applied to the surface of the Si substrate 11 exposed at the region D at 800-1100° C. As a result a thermal oxide film 12D is formed with a thickness of 5-10 nm. Along with the thermal oxidation process in the step of FIG. 8F, there occurs a growth in the thermal oxide film 12C that was formed previously in the regions B and C.
Next, the resist pattern 15B is formed in the step of FIG. 8G on the structure of FIG. 8F except for the region B, similar to the process of FIG. 1E, and the thermal oxide film 12C is removed from the surface of Si substrate 11 in region B by a wet etching processing of HF while using the resist pattern 15B as a mask.
Further, in the step of FIG. 8H, the resist pattern 15B is removed and a thermal oxidation process is applied with a temperature of 800-1100° C. As a result, the thermal oxide film 12B is formed on the surface of the Si substrate 11 in the region B with a thickness of 1.5-5 nm. Along with the thermal oxidation process of FIG. 8H, there occurs a growth in the thermal oxide film 12D on thermal oxide film 12C in correspondence to the region D.
Next, in the step of FIG. 8I corresponding to the step of FIG. 1G, the structure of FIG. 8H is covered with an amorphous silicon film 16. The amorphous silicon film 16 is then patterned in the step of FIG. 8J corresponding to FIG. 1H while using the resist pattern 17A as a mask, and the stacked gate structure 16F of the flash memory is formed in the flash-memory cell region A as a result. It should be noted that the stacked gate structure 16F includes a stacking of the amorphous silicon pattern 13A, the ONO pattern 14A and the amorphous silicon pattern 16A. In the step of FIG. 8I, on amorphous silicon film 16 a low-resistance silicide film such as WSi or CoSi may be formed according to the need.
Furthermore, an amorphous silicon film 16 is patterned in region B-D in the step of FIG. 8K that corresponds to the step of FIG. 1I by using the resist pattern 17B. As a result, the gate electrode 16B of the low-voltage transistor, the gate electrode 16C of the high-voltage transistor are formed in the regions B and region C, respectively. Further, a gate electrode 16D of the mid-voltage transistor is formed in region D.
Next, in the step of FIG. 8L corresponding to the step of FIG. 1J, the gate electrodes 16B-16D and also the stacked gate electrode structure 16A are covered by a thermal oxide film 18 formed by a thermal oxidation process. Further, by conducing the process corresponding to the steps of FIGS. 1K-1P explained previously, a semiconductor integrated circuit that integrates the flash memory cell and the low-voltage transistor and the mid-voltage transistor and the high-voltage transistor is obtained on the Si substrate 11 as shown in FIG. 8M. It should be noted that the mid-voltage transistor includes a W plug 20D that extends through the interlayer insulation film 20 as shown in FIG. 8M. Further, LDD diffusion regions 11h and highly doped diffusion regions 11i are formed in the Si substrate in correspondence to the region D. In the process of FIG. 8M, the surface of the diffusion regions 11f, 11g, on 11i may be covered with a low-resistance silicide-film of TiSi or CoSi formed by a salicide process according to the needs.
In the fabrication process of the semiconductor integrated circuit by the process of FIGS. 8A-8M, it should be noted that a structure shown in the enlarged view of FIGS. 10A-10D is obtained in the regions A-D by forming the amorphous silicon film 13 and the ONO film 14 consecutively on the tunneling oxide film 12A in the step of FIG. 8B as shown in the enlarged view of FIGS. 9A-9D, followed by the step of removal of the films 12A, 13 and 14 from the surface of the Si substrate 11 in the step of FIG. 8C in the regions B-D while using the resist pattern 15A as a mask. As a result, the exposed surface of the Si substrate is surrounded by the field the oxide film 11F as shown in FIGS. 10B-10D, in correspondence to the regions B-D. Such an exposed part forms a depression.
Next, the thermal oxidation process of FIG. 8D is conducted and a thermal oxidation is caused in the exposed surface of the Si substrate 11 in each of the regions B-D. As a result, as shown in the enlarged view of FIGS. 11A-11D, a thermal oxide film 12C is formed on the exposed surface of the Si substrate 11 in each of the regions B-D in the state that the thermal oxide film 12C protrudes slightly in the upward direction from the boundary to the surrounding field oxide film 11F. In corresponding to this, a relative depression is formed on the surface of thermal oxide film 12C along the boundary to the surrounding field oxide film 11F in each of the regions B-D.
Next, in the step of FIG. 8E, the thermal oxide film 12C protruding in the upward direction in the region D is removed by a wet etching process while using the resist pattern 15D as a mask as shown in the enlarged view of FIGS. 12A-12D. Along with this, a depression is formed with respect to the surface of Si substrate 11 so as to enclose the region D between the region D and the field oxide film 11F.
Further, in the thermal oxidation process of FIG. 8F, there occurs a growth of the thermal oxide film 12C in the regions B and C as shown in the enlarged view of FIGS. 13A-13D as a result of formation of the thermal oxide film 12D in the region D. As a result of the growth of such a thermal oxide film 12C, the step formed between the surface of the thermal oxide film 12C and the depression surrounding the thermal oxide film 12C is increased in the regions B and C. Further, the step formed between the surface of thermal oxide film 12D and the depression surrounding the thermal oxide film 12D is increased in the region D.
Thus, it will be understood that, in the event the thermal oxide film 12C covering the surface of the Si substrate 11 in the region B is removed by a wet etching process while using the resist pattern 15B as a mask in the step of FIG. 8G, the depth of the depression (circled in FIGS. 14B and 14D) formed between the Si substrate and the surrounding field oxide film 11F in the region B is increased as shown in the enlarged view of FIGS. 14A-14D, along with the decrease of thickness of the field oxide film 11F. Further, a similar deep depression is formed also in the region D along the boundary to the surrounding field oxide film 11F.
Furthermore, in the event that the amorphous silicon film 16 constituting the gate electrode is deposited on the structure of FIGS. 15A-15D in the step of FIG. 8I, the thickness of the gate insulation film 12B or 12D becomes extremely thin especially in the low-voltage transistor region B and in the mid-voltage transistor region D in the vicinity of the depression as circled in the drawings. Thus, the threshold characteristics of the MOS transistors experienced a modification in these regions.
With such reasons, the process of FIGS. 8A-8M is not used actually in the production semiconductor devices. It should be noted that the foregoing problems are more serious in a semiconductor integrated circuit that uses the STI structure 11G instead of the field oxide film 11F for the device isolation structure, as shown in FIG. 16A-16C.
Meanwhile, there is a proposal to construct a flash memory device that uses a single-layer gate electrode structure instead of the stacked gate electrode structure in a related art of the present invention.
FIG. 17 shows the construction of a flash memory cell of a single-layer gate electrode structure in a plan view, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
FIG. 17 is referred to.
It can be seen that the device region 11A is defined on the Si substrate 11 by the field oxide film 11F similarly as before. On the other hand, the floating-gate electrode pattern 13A is formed such that an end of the floating-gate electrode pattern 13A traverses the device region 11A on the Si substrate 11. Further, a source region 11a of n−-type and a source line region 11b of n+-type are formed in the device region 11A at a first side of the floating-gate electrode pattern 13A while using the floating-gate electrode pattern 13A as a self-aligned mask. Further, a drain region 11c an n+-type is formed in the device region 11A at the second side of the floating-gate electrode pattern 13A.
In the vicinity of the device region 11A, it can be seen that there is formed another device region 11B on the Si substrate 11, and an n+-type diffusion region 11C is formed in the device region 11B. Further, a coupling part 13Ac is formed at the other end of the floating-gate electrode pattern 13A so as to cover the diffusion region 11C.
FIG. 18A shows a cross-sectional view taken along a line X-X′ of FIG. 17.
FIG. 18A is referred to.
It can be seen that there is formed a tunneling oxide film 12A on the Si substrate 11 between the source region 11b and the drain region 11c and that the floating-gate electrode pattern 13A is formed on the tunneling oxide film 12A. Further, it can be seen that the source region 11a of n−-type is formed in the Si substrate 11 outside of the n+-type source region 11b. Further, it can be seen that a sidewall insulation film is formed to the sidewall surface of the floating-gate electrode pattern 13A.
FIG. 18B shows the cross-sectional view taken along a line Y-Y′ of FIG. 17.
FIG. 18B is referred to.
It can be seen that the floating-gate electrode pattern 13A extends continuously on the field oxide film 11F formed on the Si substrate 11 from the device region 11A in which the flash memory cell of FIG. 18A is formed to the device region 11AC. Thereby, the end part 13Ac of the floating-gate electrode pattern 13A forms a capacitance coupling with the highly doped diffusion region 11C through the oxide film 12Ac.
Thus, at the time of writing operation (“program”) , the source region 11b is grounded and a drain voltage of +5V is applied to the drain region as show in FIGS. 19A and 19B. Further, a writing voltage of +10V is applied to the highly doped diffusion region 11C. Thus, the potential of the floating-gate electrode 13A goes up and there occurs injection hot electrons into the floating-gate electrode 13A through the tunneling oxide film 12A in the device region 11A.
At the time of erasing operation (“erase”), on the other hand, the drain region 11c and the highly doped diffusion region 11C are grounded as shown in FIGS. 19C and 19D. Further, an erasing voltage of +15V is applied to the source region 11b. As a result, the electrons in floating-gate electrode 13A cause a tunneling into the source region 11a through the tunneling oxide film 12A and are absorbed by the source power supply through the source region 11b. 
Thus, in the flash memory of FIG. 17, the highly doped diffusion region 11C plays the role of the control gate electrode and it is not necessary to form the ONO film 14 between the polysilicon floating-gate electrode and the polysilicon control gate electrode, contrary to the conventional flash memory having the stacked gate structure explained previously. It should be noted that it is the oxide film 12Ac that plays the role of the ONO film 14 in the flash memory of FIG. 17. As the oxide film 12Ac can be formed by a thermal oxidation process on the Si substrate 11, the oxide film 12Ac is formed with high quality.
FIGS. 20A-20O are diagrams showing the fabrication process of a semiconductor integrated circuit that includes the flash memory cell of FIG. 17 in addition to the low-voltage transistor B, the mid-voltage transistor D and the high-voltage transistor C, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
FIG. 20A is referred to.
The thermal oxide film 12C is formed on the Si substrate 11 in each of the flash-memory cell region A, the low-voltage transistor region B, the mid-voltage transistor region D and the high-voltage transistor region C by a thermal oxidation processes conducted at the temperature of 800-1100° C. with a thickness of 5-50 nm. Further, the thermal oxide film 12C is removed from the flash-memory cell region A by a patterning process in the step of FIG. 20B while using a resist pattern 151.
Next, the resist pattern 151 is removed in the step of FIG. 20C, and a tunneling oxide film 12A is formed on the surface of the Si substrate 11 in correspondence to the region A with a thickness of 5-12 nm by conducting a thermal oxidation process with the temperature of 800-1100° C. In the step of FIG. 20C, there occurs a growth of the thermal oxide film 12C in each of the regions B-D as a result of the thermal oxidation process for forming the tunneling oxide film 12A.
Next, the thermal oxide film 12C is removed in the mid-voltage transistor region D by a patterning process in the step of FIG. 20D while using a resist pattern 152. Next, in the step of FIG. 20E, a thermal oxidation process is conducted, after removing the resist pattern 152, with a temperature of 800-1100° C., and the thermal oxide film 12D is on the region D with a thickness of 5-10 nm. In the step of FIG. 20E, there occurs a growth of the tunneling oxide film 12A in the region A and also a growth of the thermal oxide film 12C in the regions B and C as a result of the thermal oxidation process used for forming the thermal oxide film 12D.
Next, in the step of FIG. 20F, the thermal oxide film 12C is removed from the low-voltage transistor region B as a result of a patterning process that uses a resist pattern 153. Next, in the step of FIG. 20G, a thermal oxidation process is conducted with the temperature of 800-1100° C., and a thermal oxide film 12B is formed on the region B with the thickness of 1.5-5 nm. In the step of FIG. 20G, there also occurs a growth of the tunneling oxide film 12A in the region A, a growth of thermal oxide film 12C in the region C, and a growth of the thermal oxide film 12D in the region D, as a result of the thermal oxidation process for forming the thermal oxide film 12B.
Next, the amorphous silicon film 13 doped uniformly with P is deposited on the Si substrate 11 in the step of FIG. 20H with a thickness of 120-250 nm, followed by a patterning process in the step of FIG. 20I while using the resist pattern 171 as a mask. In this way, the floating-gate electrode pattern 13A is formed in the flash-memory cell region A, the gate electrode pattern 13B is formed in low-voltage transistor region B, the gate electrode pattern 13D is formed in mid-voltage transistor region D, and the gate electrode pattern 13C is formed in the high-voltage transistor region C.
Next, in the step of FIG. 20J, the surface of the floating-gate electrode pattern 13A and the surface of the gate electrode patterns 13B-13D are covered by a thermal oxide film 18 with a thickness of about 5-10 nm by conducting a thermal oxidation processes at 800-900° C., and an ion implantation process P+ or As+ is conducted in the step of FIG. 20K while using the resist pattern 172 as a mask. The ion implantation process is conducted under an accelerating voltage of 50-80 keV with a dose 1×10143×1014 cm−2, and the source region 11a is formed as a result.
Further, in the step of FIG. 20L, the regions B-D are covered by a resist pattern 173 and an ion implantation process of As+ is conducted into the region A while using the floating-gate electrode pattern 13A as a self-aligned mask. The ion implantation process may be conducted under an accelerating voltage of 30-50 keV with −2 of a dose 5×1014-1×1015 cm−2. As a result, the source line region 11b of n+-type is formed within the source region 11a. Further, a drain region 11c of n+-type is formed in the opposite side of the source region 11a with respect to the channel region.
Next, a resist pattern 173 is formed in the step of FIG. 20M so as to cover the flash-memory cell region A, and a p-type or n-type impurity element is introduced by a ion implantation process. As a result, the LDD region 11d is formed in the region B and the LDD region 11e is in the region C. Further, the LDD region 11h is formed to in the region D.
Further, in the step of FIG. 20N, the sidewall oxide films 16s are formed on the both sidewall surfaces of the floating-gate electrode pattern 13A and the gate electrode patterns 13B-13D. Next, in the process of FIG. 20O, the impurity element of p-type or n-type is introduced to each of the regions B-D while covering the flash memory region A by a resist pattern 174. As a result, the diffusion regions 11f-11i are formed.
In the foregoing steps of FIGS. 20A-20O, however, there arises a problem in that a deep depression is formed, as a result of repetition of thermal oxide formation and subsequent etching, along the boundary of the device regions A-D, especially along the boundary to the field oxide film 11F in each of the regions B and D as shown in the enlarged view of FIGS. 21A-21D, FIGS. 22A-22D, FIGS. 23A-23D, FIGS. 24A-24D, FIGS. 25A-25D, FIGS. 26A-26D and FIGS. 27A-27D. Because of this, there occurs a localized thinning of gate insulation film especially in the low-voltage transistor region B and in the mid-voltage transistor region D, as shown in FIGS. 27B and 27C by circles. When a MOS transistor is formed on such a region, there inevitably occurs a local modification of threshold characteristics. In the foregoing drawings, it should be noted that those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. It should be noted that the step of FIGS. 21A-21D corresponds to the step of FIG. 20A, the step of FIGS. 22A-22D corresponds to the step of FIG. 20B, the step of FIGS. 23A-23D corresponds to the step of FIG. 20C, the step of FIGS. 24A-24D correspond to the step of FIG. 20D, the step of FIGS. 25A-25D corresponds to the step of FIG. 20E, the step of FIGS. 26A-26D corresponds to the step of FIG. 20F, and the step of FIGS. 27A-27D corresponds to the step of FIG. 20G.
It should be noted that the problem of formation of the depression and modification of the threshold characteristics become serious in the semiconductor integrated circuits that have the STI device isolation structure 11G as shown in FIGS. 28A-28D. As shown in FIG. 28A, there is a tendency, in the semiconductor integrated circuit having an STI structure, in that a depression is formed in the boundary part of the device region also in the flash-memory cell region A, and there is a concern that the writing characteristics and erasing characteristics of the flash memory cell may be changed.
Further, in the step of FIGS. 20A-20O, it should be noted that the gate oxide films 12C and 12D are formed after plural thermal oxidation processes and plural resist processes. Thus, these gate oxide films generally have a stacked structure as they shown in FIGS. 29A-29C, and there may be a problem of film quality.
Furthermore, in the step of FIGS. 20A-20O, it should be noted that the tunneling oxide film 12A is formed as a stacking of plural thermal oxide films as shown in FIG. 30A. Thus, the tunneling oxide film 12A tends to include therein defects, and there is a tendency that the electric charges accumulated in the floating-gate electrode 13A are dissipated to the Si substrate 11 as show in FIG. 30B. When such a leakage occurs, the flash memory device cannot hold information over a time period prescribed by specification.